IP delivered with the Vivado® Design Suite have the following characteristics over IP delivered in the ISE® Design Suite CORE™ Generator tool:
• Are accessible in a single unified IP Catalog
• Uses the new Xilinx® Design Constraints (XDC file) for physical and timing constraints which are applied automatically
• Generates a Xilinx Constraints Interface (XCI) file, various output products and by default a synthesis Design Checkpoint (DCP file).
° The DCP contains a netlist for the IP and when referencing the XCI the netlist any constraints generated for the IP are used during implementation.
° The DCP can be used directly, similar to an NGC, as it contains both the netlist and resolved constraints, but it is not recommended.
° If an IP delivers BMM, ELF, Tcl script, or certain other files, they are not contained in the DCP. Using the XCI ensures all output products, including a synthesized netlist, are used.
• Places each IP (XCI file) in a separate directory (see the documentation on the Managed IP Flow and In Project Flow in the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 6] .
• No longer uses the XilinxCoreLib for simulation (unless using older IP) as each IP delivers its own simulation sources as an output product