1. Open the MHS file for the XPS design in a text editor.
2. Determine which interfaces are used on MicroBlaze. Search the MHS file for BUS_INTERFACE ILMB , BUS_INTERFACE DLMB , BUS_INTERFACE M_AXI_DP , BUS_INTERFACE M_AXI_DC , BUS_INTERFACE M_AXI_IC , BUS_INTERFACE DEBUG , BUS_INTERFACE INTERRUPT .
Typically, MicroBlaze designs built by the Base System Builder (BSB) contain LMB interfaces for local block RAM,
MicroBlaze Data Port interface (for slave registers, such as AXI GPIO ), debug interface (using MDM with or without UART based upon the C_USE_UART parameter in MDM IP), and interrupt support (using the AXI_INTC slave IP). In addition, BSB adds clock and reset support with the clock_generator and proc_sys_reset IP.
More complex interfaces use the MicroBlaze Instruction Cache Port and MicroBlaze Data Cache Port. Typically, these interfaces are used for high performance portions of the design that use AXI MIG or AXI block RAM (AXI4 slaves). The C_CACHE_BYTE_SIZE and C_DCACHE_BYTE_SIZE parameters determine the size of caches for the MicroBlaze MHS instance.
3. Refer to Table: Bus Interfaces Used in XPS MicroBlaze Design and set MicroBlaze Block Automation, based on the interfaces in the MHS file for the MicroBlaze instance.