Designing with a platform board selected as the part: - 2022.2 English - UG911

1. From the Board tab drag and drop the desired clock, such as the System differential clock , for the KC705 board on the block design canvas.

Figure 5-7: Board Tab

X-Ref Target - Figure 5-7

2. Likewise drag and drop the FPGA Reset from the Board tab to the block design canvas .

For more information on the platform board flow, refer to this link in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) [Ref 10] .