Connecting AXI MIG Interfaces - 2022.2 English - UG911

ISE to Vivado Design Suite Migration Guide (UG911)

Document ID
UG911
Release Date
2022-10-19
Version
2022.2 English

Right-click the following interfaces in the block diagram and select Make External for each:

SYS_CLK

sys_rst

DDR3

This provides all DDR3 signals, clocks and resets to be connected to the top-level board pins.

See the MicroBlaze Block Automation section for instructions on connecting AXI MIG to the rest of the design.