Open the MHS in a text editor to determine if AXI interfaces clocks were connected for Design Automation to function properly. A search for these clocks in the MHS includes:
M_AXI_GP0_ACLK M_AXI_GP1_ACLK S_AXI_GP0_ACLK |
S_AXI_GP1_ACLK S_AXI_ACP_ACLK S_AXI_HP0_ACLK |
S_AXI_HP1_ACLK S_AXI_HP2_ACLK S_AXI_HP3_ACLK |
Typically, these clocks are connected to FCLK_CLK(0-3) on the processing_system7 instance. If not, you must connect them to the external clk port or clk_wiz in the design that matches the configuration in the MHS. Connect these clocks based on connections in the MHS file.
In addition, if DMA Controller Peripheral request interface is included in the processing_system7 instance in the MHS, connect the following clocks, if applicable: DMA0_ACLK, DMA1_ACLK, DMA2_ACLK, DMA3_ACLK .
Typically these clocks are connected to FCLK_CLK(0-3) on the processing_system7 instance. If not, you must connect these clocks to the external clk port or clk_wiz in the design that matches the configuration in the MHS.