Clock Constraints - 2022.2 English - UG911

ISE to Vivado Design Suite Migration Guide (UG911)

Document ID
UG911
Release Date
2022-10-19
Version
2022.2 English

Period

UCF Example

NET "clka" TNM_NET = "clka";

TIMESPEC "TS_clka" = PERIOD "clka" 13.330 ns HIGH 50.00%;

XDC Example

create_clock -name clka -period 13.330 -waveform {0 6.665}\ [get_ports clka]

Period Constraints with Uneven Duty Cycle

UCF Example

NET "clka" TNM_NET = "clka";

TIMESPEC "TS_clka" = PERIOD "clka" 13.330 ns HIGH 40.00%;

XDC Example

create_clock -name clka -period 13.330 -waveform {0 5.332}\ [get_ports clka]

Generated Clocks Constraints

UCF Example

NET "gen_clk" TNM_NET = "gen_clk";

TIMESPEC "TS_gen_clk" = PERIOD "gen_clk" "TS_clka" * 0.500 HIGH 50.00%;

XDC Example

create_generated_clock -source [get_ports clka] -name gen_clk\ -multiply_by 2 [get_ports gen_clk]

Period Constraints with LOW Keyword

UCF Example

NET "clka" TNM_NET = "clka";

TIMESPEC "TS_clka" = PERIOD "clka" 13.330 ns LOW 50.00%;

XDC Example

create_clock -name clka -period 13.330 -waveform {6.665 13.330}\ [get_ports clka]

Net PERIOD Constraints

UCF Example

NET "clk_bufg" PERIOD = 10 ns;

XDC Example

create_clock -name clk_bufg -period 10 -waveform {0 5}\
[get_pins clk_bufg/O}

Note: Unless there is specific reason to define the clock on bufg/O , define it at an upstream top-level port.