This section covers adding AXI IP to the design. Design Automation provides (1) connections to Proc Sys Reset IP for reset capability and (2) proper clocks to the IP AXI Interface and to the generated AXI Interconnect instance. With the ZYNQ7 Processing System Block, there can be up to 9 AXI3 Interfaces (2xAXI3 Master interfaces/6xAXI3 Slave interfaces).