The Vivado IDE provides new users with an intuitive interface and gives advanced users the power they require. All of the tools and tool settings are written in native Tcl. You can run analysis and assign constraints throughout the design process. For example, the tools can provide timing or power estimations after synthesis, placement, or routing. Because the database is accessible through Tcl, you can make changes to constraints, design configuration, or tool settings in real time, often without forcing re-implementation.
The Vivado IDE introduces the concept of opening designs in memory. Opening a design effectively loads the design netlist at that particular stage of the design flow, assigns the constraints to the design, and applies the design to the target device. This allows you to visualize and interact with the design at each design stage. The Vivado IDE enables you to open designs after register-transfer level (RTL) elaboration, synthesis, and implementation. You can make change to constraints, logic or device configuration, and implementation results. You can also use design checkpoints to save the current state of any design. A design checkpoint is a snapshot of the design at any stage of the design process that includes the netlist, constraints, and implementation results. Vivado automatically creates design checkpoints at each stage of the flow that can be opened and analyzed.
For more information on the Vivado IDE, see the Vivado Design Suite User Guide: Using the Vivado IDE (UG893). For more information on analyzing designs, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).