Programming an FPGA or ACAP prior to debugging uses exactly the same steps as described in Programming the FPGA or ACAP. After programming the device with the .pdi file that contains the new ILA, VIO, and JTAG-to-AXI Master debug cores, the Hardware window now shows the debug cores with the RTL instance name shown in parenthesis, that were detected when scanning the device.
Figure 1. Hardware Window Showing Debug Cores
For more information on using the ILA core, refer to Setting up the ILA Core to take a Measurement. For more information on using the VIO core, refer to Setting up the VIO Core to take a Measurement.
Important: Ensure the JTAG clock is slower than the clocks input to the debug cores. You can modify the JTAG frequency using the Open New Hardware Target wizard or the following Tcl command:
set_property PARAM.FREQUENCY 250000 [get_hw_targets */xilinx_tcf/Digilent/210203327962A]