AXI4 Debug Hub - 2022.2 English - UG908

Vivado Design Suite User Guide: Programming and Debugging (UG908)
Document ID
UG908
Release Date
2022-10-19
Version
2022.2 English

On Versal® ACAP architectures the AXI4 Debug Hub is an IP core that provides an interface between the AXI4 Master interface of the CIPS and the AXI4-Stream interface on the Vivado Hardware Debug cores including the following:

  • Integrated Logic Analyzer (ILA)
  • Virtual Input/Output (VIO)
  • Soft Memory IP
Note: On Versal devices, the AXI4 Debug Hub can be manually instantiated as an IP or inserted automatically during opt_design, just as with previous architectures.