Verilog Module Example - Verilog Module Example - 2022.2 English - UG901
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English
(* DONT_TOUCH = "yes" *)
module example_dt_ver
(clk,
In1,
In2,
out1);