• Verilog-2001 attributes pass specific information to programs such as synthesis tools.
• Verilog-2001 attributes are generally accepted.
• Specify Verilog-2001 attributes anywhere for operators or signals, within module declarations and instantiations.
• Although the compiler might support other attribute declarations, Vivado synthesis ignores them.
• Use Verilog-2001 attributes to set constraints on:
° Individual objects, such as:
- Module
- Instance
- Net
° Set the following synthesis constraints:
- Full Case
- Parallel Case