VHDL and Verilog boundary rules are, as follows:
° The boundary between VHDL and Verilog is enforced at the design unit level.
° A VHDL entity or architecture can instantiate a Verilog module. See Instantiating VHDL in Verilog in the following section.
° A Verilog module can instantiate a VHDL entity. See Instantiating Verilog in VHDL .