VHDL Legacy Packages - VHDL Legacy Packages - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English

std_logic_arith (Synopsys)

° Unsigned and signed vector types based on std_logic .

° Overloaded arithmetic operators, conversion functions, and extended functions for these types.

std_logic_unsigned (Synopsys)

° Unsigned arithmetic operators for std_logic and std_logic_vector

std_logic_signed (Synopsys)

° Signed arithmetic operators for std_logic and std_logic_vector

std_logic_misc (Synopsys)

° Supplemental types, subtypes, constants, and functions for the std_logic_1164 package, such as and_reduce and or_reduce .