VHDL Component Configuration - VHDL Component Configuration - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English

A component configuration explicitly links a component with the appropriate model.

A model is an entity and architecture pair.

Vivado synthesis supports component configuration in the declarative part of the architecture. The following is an example:

for instantiation_list : component_name use

LibName.entity_Name(Architecture_Name);

The following statement indicates that:

All NAND2 components use the design unit consisting of entity NAND2 and architecture ARCHI.

The design unit is compiled in the work library.

For all : NAND2 use entity work.NAND2(ARCHI);

The value of the top module name ( -top ) option in the synth_design command is the configuration name instead of the top-level entity name.