VHDL Architecture Declaration Coding Example - VHDL Architecture Declaration Coding Example - 2022.2 English

VHDL Architecture Declaration Coding Example - VHDL Architecture Declaration Coding Example - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2022-11-16

Version

2022.2 English

ibrary IEEE;

use IEEE.std_logic_1164.all;

entity EXAMPLE is

port (

A,B,C : in std_logic;

D,E : out std_logic );

end EXAMPLE;

architecture ARCHI of EXAMPLE is

signal T : std_logic;

begin

...

end ARCHI;