Vivado synthesis supports sequential always blocks.
• Describe a sequential circuit with an always block and a sensitivity list that contains the following edge-triggered (with posedge or negedge ) events:
° A mandatory clock event
° Optional set/reset events (modeling asynchronous set/reset control logic)
• If no optional asynchronous signal is described, the always block is structured as follows:
always @(posedge CLK)
begin
<synchronous_part>
end
• If optional asynchronous control signals are modeled, the always block is structured as follows:
always @(posedge CLK or posedge ACTRL1 or à )
begin
if (ACTRL1)
<$asynchronous part>
else
<$synchronous_part>
end