Unsupported Verilog Gate Level Primitives - Unsupported Verilog Gate Level Primitives - 2022.2 English

Unsupported Verilog Gate Level Primitives - Unsupported Verilog Gate Level Primitives - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2022-11-16

Version

2022.2 English

The following table lists the gate-level primitives that are not supported in Vivado synthesis.