USE_DSP Example (Verilog) - USE_DSP Example (Verilog) - 2022.2 English - UG901
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English
(* use_dsp = "yes" *) module test(clk, in1, in2, out1);