USE_DSP Example (VHDL) - USE_DSP Example (VHDL) - 2022.2 English - UG901
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English
attribute use_dsp : string;
attribute use_dsp of P_reg : signal is "no"