Targeting SystemVerilog for a Specific File - Targeting SystemVerilog for a Specific File - 2022.2 English

Targeting SystemVerilog for a Specific File - Targeting SystemVerilog for a Specific File - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2022-11-16

Version

2022.2 English

By default, the Vivado synthesis tool compiles *.v files with the Verilog 2005 syntax and *.sv files with the SystemVerilog syntax.

To target SystemVerilog for a specific *.v file in the Vivado IDE, right-click the file, and select Source Node Properties . In the Source File Properties window, change the File Type to SystemVerilog , and click OK .