Syntax (VHDL) - Syntax (VHDL) - 2022.2 English - UG901

To set this attribute, place the proper VHDL attribute syntax on the signal in question.

Declare the VHDL attribute as follows:

attribute MARK_DEBUG : string;

Specify the VHDL attribute as follows:

attribute MARK_DEBUG of signal_name : signal is "{TRUE|FALSE}";

Where signal_name is an internal signal.