Syntax Example (Verilog) - Syntax Example (Verilog) - 2022.2 English - UG901
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English
// Marks an internal wire for debug
(* MARK_DEBUG = "TRUE" *) wire debug_wire,