Single-Port Block RAM Write-First Mode (Verilog) - Single-Port Block RAM Write-First Mode (Verilog) - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English

Filename: rams_sp_wf.v

// Single-Port Block RAM Write-First Mode (recommended template)

// File: rams_sp_wf.v

module rams_sp_wf (clk, we, en, addr, di, dout);

input clk;

input we;

input en;

input [9:0] addr;

input [15:0] di;

output [15:0] dout;

reg [15:0] RAM [1023:0];

reg [15:0] dout;

always @(posedge clk)

begin

if (en)

begin

if (we)

begin

RAM[addr] <= di;

dout <= di;

end

else

dout <= RAM[addr];

end

end

endmodule