Real Numbers - Real Numbers - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English

Synthesis supports real numbers; however, they cannot be used to create logic. They can only be used as parameter values. The SystemVerilog-supported real types are:

• real

• shortreal

• realtime