ROM_STYLE Example (Verilog) - ROM_STYLE Example (Verilog) - 2022.2 English - UG901
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English
(* rom_style = "distributed" *) reg [data_size-1:0] myrom [2**addr_size-1:0];