RETIMING_BACKWARD Example (VHDL) - RETIMING_BACKWARD Example (VHDL) - 2022.2 English - UG901
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English
attribute retiming_backward : integer;
attribute retiming_backward of my_sig : signal is 1;