RAM Inference - Simple Dual Port Structure (SystemVerilog) - RAM Inference - Simple Dual Port Structure (SystemVerilog) - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English

Filename: rams_sdp_struct.sv

// RAM Inference using Struct in SV(Simple Dual port)

// File:rams_sdp_struct.sv

typedef struct packed {

logic [3:0] addr;

logic [27:0] data;

} Packet;

module rams_sdp_struct #(

parameter A_WID = 10,

D_WID = 32

)

(

input clk,

input we,

input ena,

input [A_WID-1:0] raddr, waddr,

input Packet din,

output Packet dout

);

Packet mem [2**A_WID-1:0];

always @ (posedge clk)

begin

if (ena) begin

if(we)

mem[waddr] <= din;

end

end

always @ (posedge clk)

begin

if (ena) begin

dout <= mem[raddr];

end

end

endmodule