When a Verilog module is instantiated in a VHDL entity or architecture, formal ports can have the following characteristics:
• Allowed directions are: input , output , and inout .
• Allowed data types are: wire and reg
• Vivado synthesis does not support:
° Connection to bidirectional pass options in Verilog.
° Unnamed Verilog ports for mixed language boundaries.
Use an equivalent component declaration to connect to a case sensitive port in a Verilog module. Vivado synthesis assumes Verilog ports are in all lowercase.