When a VHDL entity is instantiated in a Verilog module, formal ports can have the following characteristics:
•
Allowed directions:
in
,
out
,
inout
•
Unsupported directives:
buffer
,
linkage
•
Allowed data types:
bit
,
bit_vector
,
std_logic
,
std_ulogic
,
std_logic_vector
,
std_ulogic_vector