PARALLEL_CASE specifies that the case statement must be built as a parallel structure. Logic is not created for an if -elsif structure. Because this attribute affects the compiler and the logical behavior of the design, it can be set in the RTL only.
(* parallel_case *) case select
3’b100 : sig = val1;
3’b010 : sig = val2;
3’b001 : sig = val3;
endcase
IMPORTANT: This attribute can only be controlled through the Verilog RTL.