• A Behavioral Verilog module declaration consists of:
° The module name
° A list of circuit I/O ports
° The module body in which you define the intended functionality
• End with an endmodule statement.
• A Behavioral Verilog module declaration consists of:
° The module name
° A list of circuit I/O ports
° The module body in which you define the intended functionality
• End with an endmodule statement.