MAX_FANOUT Example (VHDL) - MAX_FANOUT Example (VHDL) - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English

signal sig1 : std_logic;

attribute max_fanout : integer;

attribute max_fanout of sig1 : signal is 50;

Note: In VHDL, max_fanout is an integer.