KEEP_HIERARCHY Example (Verilog) - KEEP_HIERARCHY Example (Verilog) - 2022.2 English - UG901

On Module:

(* keep_hierarchy = "yes" *) module bottom (in1, in2, in3, in4, out1, out2);

On Instance:

(* keep_hierarchy = "yes" *)bottom u0 (.in1(in1), .in2(in2), .out1(temp1));