IOB Example (VHDL) - IOB Example (VHDL) - 2022.2 English

IOB Example (VHDL) - IOB Example (VHDL) - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2022-11-16

Version

2022.2 English

signal sig1:std_logic;

attribute IOB: string;

attribute IOB of sig1 : signal is "true";