GATED_CLOCK Example (VHDL) - GATED_CLOCK Example (VHDL) - 2022.2 English - UG901

entity test is port (

in1, in2 : in std_logic_vector(9 downto 0);

en : in std_logic;

clk : in std_logic;

out1 : out std_logic_vector( 9 downto 0));

attribute gated_clock : string;

attribute gated_clock of clk : signal is "yes";

end test;