Flip-Flops and Registers Inference - Flip-Flops and Registers Inference - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English

Vivado synthesis infers four types of register primitives depending on how the HDL code is written:

• FDCE : D flip-flop with Clock Enable and Asynchronous Clear

• FDPE : D flip-flop with Clock Enable and Asynchronous Preset

• FDSE : D flip-flop with Clock Enable and Synchronous Set

• FDRE : D flip-flop with Clock Enable and Synchronous Reset