FSM_ENCODING Example (Verilog) - FSM_ENCODING Example (Verilog) - 2022.2 English - UG901
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English
(* fsm_encoding = "one_hot" *) reg [7:0] my_state;