The ( === ) and ( !== ) operators in the following table are:
• Special comparison operators.
• Used in simulation to see if a variable is assigned a value of (x) or (z).
• Treated as (==) or (!=) by synthesis.
See this link to the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 11] for more information about Verilog format for Vivado simulation.