EXTRACT_RESET Example (VHDL) - EXTRACT_RESET Example (VHDL) - 2022.2 English

EXTRACT_RESET Example (VHDL) - EXTRACT_RESET Example (VHDL) - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2022-11-16

Version

2022.2 English

signal my_reg : std_logic;

attribute extract_reset : string;

attribute extract_reset of my_reg: signal is "no";