Dual-Port Block RAM with Two Write Ports in Read First Mode Example (Verilog) - Dual-Port Block RAM with Two Write Ports in Read First Mode Example (Verilog) - 2022.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English

Filename: ram_tdp_rf_rf.v

// Dual-Port Block RAM with Two Write Ports

// File: rams_tdp_rf_rf.v

module rams_tdp_rf_rf (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);

input clka,clkb,ena,enb,wea,web;

input [9:0] addra,addrb;

input [15:0] dia,dib;

output [15:0] doa,dob;

reg [15:0] ram [1023:0];

reg [15:0] doa,dob;

always @(posedge clka)

begin

if (ena)

begin

if (wea)

ram[addra] <= dia;

doa <= ram[addra];

end

end

always @(posedge clkb)

begin

if (enb)

begin

if (web)

ram[addrb] <= dib;

dob <= ram[addrb];

end

end

endmodule