There are three main ways to instantiate and connect modules:
• The first two are by ordered list and by name, as in Verilog.
• The third is by named ports.
If the names of the ports of a module match the names and types of signals in an instantiating module, the lower-level module can by hooked up by name. For example:
module lower (
output [4:0] myout;
input clk;
input my_in;
input [1:0] my_in2;
... ...
endmodule
//in the instantiating level.
lower my_inst (.myout, .clk, .my_in, .my_in2);