Behavioral Verilog Module Declaration Example Two - Behavioral Verilog Module Declaration Example Two - 2022.2 English - UG901
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English
module example ( input A, inputB, output O
);
assign O = A & B;
endmodule