ASYNC_REG Verilog Example - ASYNC_REG Verilog Example - 2022.2 English - UG901
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-11-16
Version
2022.2 English
(* ASYNC_REG = "TRUE" *) reg [2:0] sync_regs;