32-Bit Dynamic Shift Registers Coding Example (Verilog) - 32-Bit Dynamic Shift Registers Coding Example (Verilog) - 2022.2 English - UG901

Filename: dynamic_shift_registers_1.v

// 32-bit dynamic shift register.

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// File: dynamic_shift_registers_1.v

module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);

parameter SELWIDTH = 5;

input CLK, CE, SI;

input [SELWIDTH-1:0] SEL;

output DO;

localparam DATAWIDTH = 2**SELWIDTH;

reg [DATAWIDTH-1:0] data;

assign DO = data[SEL];

always @(posedge CLK)

begin

if (CE == 1'b1)

data <= {data[DATAWIDTH-2:0], SI};

end

endmodule