Vivado Design Suite User Guide: Synthesis (UG901) - 2022.2 English - Details using Vivado® synthesis to transform an RTL design into a gate-level netlist for implementation in a Xilinx® FPGA, using SystemVerilog, Verilog, and VHDL. Describes the use of Vivado synthesis in Project and Non-Project Modes, employing multiple synthesis strategies and design constraints. - UG901

Document ID

UG901

Release Date

2022-11-16

Version

2022.2 English