Interfacing with the System Designer - 2022.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

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2022.2 English

As part of the iterative I/O and clock planning process, you can exchange information about the Xilinx® device pinout with the PCB or system designer by exporting the CSV files and IBIS models. Depending on PCB or design specification changes, you might need to reimport the pinout as described in Defining and Configuring I/O Ports. After completing the steps in the I/O and clock planning flow, you can return the pinout, along with device models for signal integrity analysis, using the CSV file and IBIS models.