I/O Planning for UltraScale Architecture Memory IP - 2022.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

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2022.2 English

UltraScale™ architecture Memory IP defines a memory controller using a pre-engineered controller and physical layer (PHY) for interfacing FPGA user designs and AMBA® specification advanced extensible interface (AXI4) slave interfaces to supported external memory devices. High-speed memory interfaces must adhere to:

  • Specific pinout requirements driven by clocking and skew needs
  • Specific rules for byte lane usage within the I/O banks for memory
  • Physical pin assignment requirements

Memory also has hard memory controller only I/O pins (DDRMC). These pins cannot be used for anything other than the hard memory controller. So if the design does not use these pins, those pins cannot be used for GPIO.

For performance purposes, the final configuration of the Memory IP is dependent on the I/O assignments. Therefore, you cannot complete final implementation of the IP until after the IP’s I/Os are assigned. For this reason, you must handle the I/O assignment and implementation of this IP differently from most other IP. This chapter describes the process for I/O planning and implementation of UltraScale architecture Memory IP.

Important: This chapter covers UltraScale architecture Memory IP only. For information on Memory IP for 7 series devices, see the Zynq-7000 SoC and 7 series Devices Memory Interface Solutions (UG586).