Input File | File Type | Description |
---|---|---|
Design Source Files |
|
|
I/O Port Lists | CSV |
|
Module-Level Netlists and Cores |
|
Note: NGC format files are not supported
in the Vivado Design Suite for
UltraScaleā¢
devices. Xilinx
recommends that you regenerate the IP using the Vivado Design Suite IP customization tools with
native output products. Alternatively, you can use the NGC2EDIF
command to migrate the NGC file to EDIF format for importing, as
described in the ISE to
ISE to Vivado Design Suite Migration
Guide (UG911). However, Xilinx
recommends using native Vivado IP rather
than XST-generated NGC format files going forward.
|
Top-Level Netlists |
|
|
Xilinx IP and IP integrator Block Designs |
|
|
Constraint Files |
|
|
Other Files |
|
BMM: Block RAM Memory Map (BMM) file is a text file that syntactically describes how
individual block RAMs make up a contiguous logical data
space. ELF: An Executable and Linkable Format (ELF) file is a binary data file that contains an executable CPU code image ready for running on a CPU. MIF: This file describes the memory contents that are used by a core, a cell, or simulation models. COE: This file describes the initial memory and coefficients contents as input for core generation. |