Additional Resources and Legal Notices - 2022.2 English - UG888

Vivado Design Suite Tutorial: Design Flows Overview (UG888)

Document ID: UG888
Release Date: 2022-11-09
Version: 2022.2 English

Vivado Design Flows Overview
Working in Project Mode and Non-Project Mode
Non-Project Mode
Project Mode
Using Tcl Commands
Tutorial Design Description
Hardware and Software Requirements
Preparing the Tutorial Design Files
Using the Non-Project Design Flow
Step 1: Examine the Example Script
Step 2: Starting Vivado with the Example Design
Step 3: Synthesizing the Design
Step 4: Launching the Vivado IDE
Step 5: Defining Timing Constraints and I/O Planning
Define Timing Constraints
I/O Planning
Step 6: Exporting the Modified Constraints
Step 7: Implementing the Design
Step 8: Opening a Design Checkpoint
Step 9: Analyzing Implementation Results
Step 10: Exiting the Vivado Tool
Using the Project Design Flow
Step 1: Creating a Project
Launch Vivado
Create a New Project
Step 2: Using the Sources Window and Text Editor
Explore the Sources Window and Project Summary
Explore the Text Editor
Step 3: Elaborating the RTL Design
Step 4: Using the IP Catalog
Step 5: Running Behavioral Simulation
Step 6: Reviewing Design Run Settings
Step 7: Synthesizing and Implementing the Design
Step 8: Analyzing the Synthesized Design
Step 9: Analyzing the Implemented Design
Open the Implemented Design
Analyze Routing
Step 10: Generating a Bitstream File
Summary
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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